FPGA Engineer required to develop state of the art video processing, distribution and interfacing systems. You will join a team of creative hardware engineers, designing video products and developing new products in high-performance real-time video. You will design and test digital video processing products using application processors and FPGAs and be responsible for FPGA IP development and integration of video processing, distribution and control logic.
This includes integration of vendor or locally produced IP, logic and algorithm implementation in RTL, constraint management, synthesis, place and route, simulation, test and debug using the latest FPGA development tools.
Key Skills
FPGA technology including VHDL. Embedded design, low level hardware and systems. CAE tools. First Degree (or equivalent) qualification in electronics or another relevant subject. Hardware design engineering commercial experience. FPGA peripheral interfaces: PCIe, DDR3/4, high-speed transceivers. Video interfaces: HDMI, HDCP, DisplayPort.
Role Responsibilities
Work with managers and senior technical staff to develop digital products and their associated designs. Advising on board level design for FPGA power-supply specification, I/O pin placement signal type, board bring-up and hardware debug.
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This includes integration of vendor or locally produced IP, logic and algorithm implementation in RTL, constraint management, synthesis, place and route, simulation, test and debug using the latest FPGA development tools.
Key Skills
FPGA technology including VHDL. Embedded design, low level hardware and systems. CAE tools. First Degree (or equivalent) qualification in electronics or another relevant subject. Hardware design engineering commercial experience. FPGA peripheral interfaces: PCIe, DDR3/4, high-speed transceivers. Video interfaces: HDMI, HDCP, DisplayPort.
Role Responsibilities
Work with managers and senior technical staff to develop digital products and their associated designs. Advising on board level design for FPGA power-supply specification, I/O pin placement signal type, board bring-up and hardware debug.
#J-18808-Ljbffr
