Ph.D. in Electrical Engineering or Physics or related engineering discipline, or Master’s in Electrical Engineering or Physics or related engineering discipline with 3+ years of experience Fundamental knowledge of semiconductor device physics related to compact modeling of different types of devices Proven experience in deep submicron CMOS and BCD device measurement and characterization with parametric analyzer, LCR meter, etc. Detailed knowledge in using manual, semi-automatic, and automatic probers Familiar with active and passive devices in CMOS and BCD process technologies Understanding of semiconductor device noise and matching behaviors Familiar with physics of semiconductor device aging Experience in test structure layout of individual devices and arrays Experience in SPICE model generation and QA flow Excellent verbal communication skills and technical writing skills Preferred Skills and Qualifications
Ability to stress test devices to understand post-stress behavior and SOA Prior experience with digital and analog design flow and methodology is a plus Experience running simulations using Cadence ADE Knowledge and experience in test structure layouts for various technology nodes, including advanced CMOS and BCD/HV for Analog/Mixed-Signal products Coding skills in Python, Perl or other computing languages At Cirrus Logic, we believe that diversity drives innovation, and we are committed to encouraging an open and collaborative culture where different approaches, ideas, and points of view are respected and valued. We aim to promote a workplace where everyone can contribute irrespective of race, colour, national origin, religion or belief, gender or gender identity, sexual orientation, age, marital status, pregnancy status, or disability.
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