We are seeking a Verification Engineer with 10+ years of industry experience to join our growing verification team.
You will have the opportunity to work on a variety of challenging and exciting projects, leading the verification process and driving innovative solutions for customers.
Key Responsibilities
Lead and support customer and internal verification projects using advanced methodologies such as Universal Verification Methodology (UVM), SystemVerilog, constrained random, coverage driven, and assertion-based techniques. Develop and implement comprehensive verification strategies, including architecting test environments, creating test benches, models, assertions, and functional tests. Own the verification process, ensuring high quality execution across projects and collaborating with teams to meet customer requirements. Mentor and lead junior engineers in the verification process, while also managing the progress and performance of verification tasks. Skills
1st or 2.1 degree in Electronics, Physics, or Computer Science from a Tier 1 University. 10+ years of experience working in verification, with a strong background in UVM and SystemVerilog. Expertise in constrained random verification, code coverage analysis, regression testing, and verification infrastructures. Experience as a verification lead, responsible for planning and executing verification strategies. VHDL or Verilog RTL experience. Mentor Questa and Cadence Incisive.
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You will have the opportunity to work on a variety of challenging and exciting projects, leading the verification process and driving innovative solutions for customers.
Key Responsibilities
Lead and support customer and internal verification projects using advanced methodologies such as Universal Verification Methodology (UVM), SystemVerilog, constrained random, coverage driven, and assertion-based techniques. Develop and implement comprehensive verification strategies, including architecting test environments, creating test benches, models, assertions, and functional tests. Own the verification process, ensuring high quality execution across projects and collaborating with teams to meet customer requirements. Mentor and lead junior engineers in the verification process, while also managing the progress and performance of verification tasks. Skills
1st or 2.1 degree in Electronics, Physics, or Computer Science from a Tier 1 University. 10+ years of experience working in verification, with a strong background in UVM and SystemVerilog. Expertise in constrained random verification, code coverage analysis, regression testing, and verification infrastructures. Experience as a verification lead, responsible for planning and executing verification strategies. VHDL or Verilog RTL experience. Mentor Questa and Cadence Incisive.
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