La Fosse is working with a Global Semiconductor company to work within their implementation team, who will work with multiple divisions across the company to steer product direction, define high-quality standards, and help drive partner success. We use our keen analytical skills and effective communication to provide solutions to a wide range of problems in the physical design space.
The successful applicant will play a key role in ensuring optimal performance and power efficiency for sophisticated semiconductor designs!
Responsibilities:
Develop and verify power intent for system level designs and SoCs Deliver accurate results across a range of technology nodes to demonstrate the best of our designs Collaborate with our chip design partners to support their physical implementation success Develop and deploy new methodologies to improve implementation efficiency and results Convert ground-breaking R&D concepts into real solutions
Required skills and experience:
Strong understanding of power management techniques and low-power design methodologies Proficiency in writing and verifying UPF (Unified Power Format) to work with industry-standard EDA tools (e.g. Synopsys, Cadence, Siemens) Experience with low power design techniques, such as clock and power gating, voltage/frequency scaling, retention The ability to analyse problems, reason logically about solutions and chart the appropriate course to take Experience in architecting and embracing new silicon implementation techniques and methodologies Be able to dream big, explore novel concepts and communicate them clearly Algorithmic thinking, with well-tested programming ability in Tcl, Make and Linux shell
'Nice to have' skills & experience:
Knowledge of microprocessor architecture, IP and SoCs Past experience with programming languages for data processing and presentation - along the lines of Python, R, Go, MatLab Experience with RTL design in an HDL such as Verilog, SystemVerilog or VHDL A STEM degree in a relevant field, such as electronics engineering or computer science
If you are interested in the role, please send your CV to [emailprotected]
#J-18808-Ljbffr
The successful applicant will play a key role in ensuring optimal performance and power efficiency for sophisticated semiconductor designs!
Responsibilities:
Develop and verify power intent for system level designs and SoCs Deliver accurate results across a range of technology nodes to demonstrate the best of our designs Collaborate with our chip design partners to support their physical implementation success Develop and deploy new methodologies to improve implementation efficiency and results Convert ground-breaking R&D concepts into real solutions
Required skills and experience:
Strong understanding of power management techniques and low-power design methodologies Proficiency in writing and verifying UPF (Unified Power Format) to work with industry-standard EDA tools (e.g. Synopsys, Cadence, Siemens) Experience with low power design techniques, such as clock and power gating, voltage/frequency scaling, retention The ability to analyse problems, reason logically about solutions and chart the appropriate course to take Experience in architecting and embracing new silicon implementation techniques and methodologies Be able to dream big, explore novel concepts and communicate them clearly Algorithmic thinking, with well-tested programming ability in Tcl, Make and Linux shell
'Nice to have' skills & experience:
Knowledge of microprocessor architecture, IP and SoCs Past experience with programming languages for data processing and presentation - along the lines of Python, R, Go, MatLab Experience with RTL design in an HDL such as Verilog, SystemVerilog or VHDL A STEM degree in a relevant field, such as electronics engineering or computer science
If you are interested in the role, please send your CV to [emailprotected]
#J-18808-Ljbffr
