Length: Initial 3 months
Location: Guildford
Hybrid: 3 days onsite p/w
IR35 Status: Small company exemption
Requirements: 10+ years experience with FPGA development including Xilinx FPGAs with design tools such as Vivado
Strong HDL Programming (VHDL/Verilog)
Experience in the development of Ethernet (10/25/100G / TCP/IP) protocols
SFP interface expertise such as I2C buses.
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