For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career!
The Engineer is responsible for I/O library development, encompassing the design, simulation, characterization, and validation of I/O pad libraries. Also responsible for defining the ESD methodology and specifying the chip and IP level ESD requirements. Design ESD protection devices and circuits to meet design requirements. Develop test structures to characterize Si for ESD/LUP properties. Drive the development of design rules based on Si characterization data. Interface with Foundry on ESD library and ESD/LUP rule development activities. The engineer needs to have a holistic view of ESD/EOS protection for mixed-signal CMOS circuits and the ability to pull pieces together to ensure no gaps or blind spots in strategy.
Responsibilities
Design, simulate, and optimize I/O circuits and ESD structures Characterization and modeling of I/O libraries to support mixed-signal design flow Release and maintain I/O libraries and models Must understand ESD and latch-up requirements Drive ESD sign-off methodology for chip & block-level projects Technical lead capable of pulling together engineer’s new & existing methodologies to tie ESD-Latch up-IO methodologies together & get buy-in from BU’s Required Skills and Qualifications
MSc EE and relevant proven experience Holistic view of ESD/EOS protection for mixed-signal CMOS circuits Strong fundamentals in ESD circuit design, layout, and testing Relevant experience in IO design, including CMOS circuit design, ESD and latch-up requirements, physical verification, and characterization Chip-level ESD signoff experience Must understand layout and be able to guide layout engineers Proficiency with Cadence schematic capture, layout, and simulation tools Ability to work independently and lead or be part of a technical team Effective oral and written communication Preferred Skills and Qualifications
Experience in IBIS model generation is a plus
This position is based in Edinburgh, UK. This is a hybrid remote position and will follow a 2+ day in-office work schedule, with in-office days based on business needs and team preference. You must be based within commutable distance of the work location listed on the job posting, or willing to relocate prior to beginning employment with Cirrus Logic. #LI-Hybrid #LI-PD1 At Cirrus Logic, we believe that diversity drives innovation, and we are committed to encouraging an open and collaborative culture where different approaches, ideas, and points of view are respected and valued. We aim to promote a workplace where everyone can contribute irrespective of race, colour, national origin, religion or belief, gender or gender identity, sexual orientation, age, marital status, pregnancy status, or disability.
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Responsibilities
Design, simulate, and optimize I/O circuits and ESD structures Characterization and modeling of I/O libraries to support mixed-signal design flow Release and maintain I/O libraries and models Must understand ESD and latch-up requirements Drive ESD sign-off methodology for chip & block-level projects Technical lead capable of pulling together engineer’s new & existing methodologies to tie ESD-Latch up-IO methodologies together & get buy-in from BU’s Required Skills and Qualifications
MSc EE and relevant proven experience Holistic view of ESD/EOS protection for mixed-signal CMOS circuits Strong fundamentals in ESD circuit design, layout, and testing Relevant experience in IO design, including CMOS circuit design, ESD and latch-up requirements, physical verification, and characterization Chip-level ESD signoff experience Must understand layout and be able to guide layout engineers Proficiency with Cadence schematic capture, layout, and simulation tools Ability to work independently and lead or be part of a technical team Effective oral and written communication Preferred Skills and Qualifications
Experience in IBIS model generation is a plus
This position is based in Edinburgh, UK. This is a hybrid remote position and will follow a 2+ day in-office work schedule, with in-office days based on business needs and team preference. You must be based within commutable distance of the work location listed on the job posting, or willing to relocate prior to beginning employment with Cirrus Logic. #LI-Hybrid #LI-PD1 At Cirrus Logic, we believe that diversity drives innovation, and we are committed to encouraging an open and collaborative culture where different approaches, ideas, and points of view are respected and valued. We aim to promote a workplace where everyone can contribute irrespective of race, colour, national origin, religion or belief, gender or gender identity, sexual orientation, age, marital status, pregnancy status, or disability.
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