Principal Analog Design Engineer
This role requires involvement in the full analogue IC design flow from specification, feasibility, through to design, simulation, documentation, and assessment of silicon results.
You will have a strong desire to develop and explore new technologies and demonstrate good analysis and problem-solving skills to develop novel and innovative solutions in the field of on-die monitoring. This will be combined with a proficiency to produce high-quality results to a schedule.
Job Responsibilities:
Architect and document novel and innovative circuit design approaches for on-die monitoring.
Identify and refine circuit implementations to achieve optimal power, area, and performance targets.
Propose design and verification strategies that efficiently use simulator features to ensure the highest quality design.
Oversee physical layout to minimize the effect of parasitics, device stress, and process variation.
Collaborate with digital RTL engineers on the development of calibration, adaptation, and control algorithms for analog circuits.
Present simulation data for peer and customer review.
Analyse and document silicon test data reports.
Mentor and review the progress of junior and mid-senior engineers.
Document design features and test plans.
Consult on the electrical characterization of your circuit within the PVT IP products.
Support customer engagements through technical review meetings and presentations.
Job Requirements:
PhD with 8-10+ years, or MSc with 10-12+ years of analog design experience.
In-depth familiarity with transistor-level circuit design - sound CMOS design fundamentals.
Ability to drive design from concept to product.
Detailed design experience with several of the following analog sub-circuits:
Voltage-controlled oscillator, bandgap reference, ADC, low voltage circuits, high precision amplifiers, voltage regulators, low leakage circuit design techniques.
Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects.
Awareness of ESD issues (i.e., circuit techniques, layout).
Good understanding of design for reliability (i.e., electro-migration, IR, aging, etc.).
Experience with EDA tools for schematic entry, physical layout, and design verification.
Knowledge of SPICE simulators and simulation methods.
Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
Experience with TCL, Perl, C, Python, MATLAB is a plus.
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You will have a strong desire to develop and explore new technologies and demonstrate good analysis and problem-solving skills to develop novel and innovative solutions in the field of on-die monitoring. This will be combined with a proficiency to produce high-quality results to a schedule.
Job Responsibilities:
Architect and document novel and innovative circuit design approaches for on-die monitoring.
Identify and refine circuit implementations to achieve optimal power, area, and performance targets.
Propose design and verification strategies that efficiently use simulator features to ensure the highest quality design.
Oversee physical layout to minimize the effect of parasitics, device stress, and process variation.
Collaborate with digital RTL engineers on the development of calibration, adaptation, and control algorithms for analog circuits.
Present simulation data for peer and customer review.
Analyse and document silicon test data reports.
Mentor and review the progress of junior and mid-senior engineers.
Document design features and test plans.
Consult on the electrical characterization of your circuit within the PVT IP products.
Support customer engagements through technical review meetings and presentations.
Job Requirements:
PhD with 8-10+ years, or MSc with 10-12+ years of analog design experience.
In-depth familiarity with transistor-level circuit design - sound CMOS design fundamentals.
Ability to drive design from concept to product.
Detailed design experience with several of the following analog sub-circuits:
Voltage-controlled oscillator, bandgap reference, ADC, low voltage circuits, high precision amplifiers, voltage regulators, low leakage circuit design techniques.
Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects.
Awareness of ESD issues (i.e., circuit techniques, layout).
Good understanding of design for reliability (i.e., electro-migration, IR, aging, etc.).
Experience with EDA tools for schematic entry, physical layout, and design verification.
Knowledge of SPICE simulators and simulation methods.
Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
Experience with TCL, Perl, C, Python, MATLAB is a plus.
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