One of the world’s leading precision timing ICs manufacturers. To complement their growing ASIC team, they are looking for an experienced analog IC designer with the skills and enthusiasm to significantly enhance my client’s competitive position by delivering robust, high performance custom analogue and mixed signal integrated circuits. To complement its growing ASIC team in the UK, they are looking for an experienced Analog ASIC Verification Engineer with the skills and enthusiasm to significantly enhance its competitive position.
About The Job
As a member of the AISC Design Engineering Department, you will join the group responsible for the development of ASICs used within its leading-edge frequency control products. You will join the very successful team that has been delivering these solutions for more than two decades. Responsibilities will include:
Perform verification simulations and generate design documents to capture key results and performance at block level, sub-system and system level for peer review and future reference for active ASIC development projects. Design suitable test benches in both Virtuoso Analog Design Environment with supporting Verilog A as required. Record and present circuit schematics, simulation test benches, test configuration and simulation results for review and assessment by the ASIC project team. Flag any performance issues early in the design cycle. Generate verification reports and design documents for all key blocks. Lead/participate in peer design reviews. Contribute to ASIC operation manual. Contribute to any continuous improvement initiatives. Ideally you will have:
A degree (BEng/MEng) in Electronic/Electrical Engineering. 5+ years’ experience in Analog circuit design or verification. Fluent with Cadence tool suites: predominantly analogue (Virtuoso) but with experience of the digital flow. Some experience in analogue circuit verification practices in CMOS and Bi-CMOS technologies or relevant industry in a development role. Ability to extract simulation results, capture them in a document and present them to the team for peer review. Proficient user of at least one scripting language. Experience in working with cross-functional teams. A working knowledge and understanding of quality systems such as ISO. To know more about this position, then
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As a member of the AISC Design Engineering Department, you will join the group responsible for the development of ASICs used within its leading-edge frequency control products. You will join the very successful team that has been delivering these solutions for more than two decades. Responsibilities will include:
Perform verification simulations and generate design documents to capture key results and performance at block level, sub-system and system level for peer review and future reference for active ASIC development projects. Design suitable test benches in both Virtuoso Analog Design Environment with supporting Verilog A as required. Record and present circuit schematics, simulation test benches, test configuration and simulation results for review and assessment by the ASIC project team. Flag any performance issues early in the design cycle. Generate verification reports and design documents for all key blocks. Lead/participate in peer design reviews. Contribute to ASIC operation manual. Contribute to any continuous improvement initiatives. Ideally you will have:
A degree (BEng/MEng) in Electronic/Electrical Engineering. 5+ years’ experience in Analog circuit design or verification. Fluent with Cadence tool suites: predominantly analogue (Virtuoso) but with experience of the digital flow. Some experience in analogue circuit verification practices in CMOS and Bi-CMOS technologies or relevant industry in a development role. Ability to extract simulation results, capture them in a document and present them to the team for peer review. Proficient user of at least one scripting language. Experience in working with cross-functional teams. A working knowledge and understanding of quality systems such as ISO. To know more about this position, then
#J-18808-Ljbffr
