Senior Design Verification Engineer

Senior Design Verification Engineer focuses on collaborate with design and architecture teams to create test plans for highly configurable ips meant to provide interconnectivity between components across an soc, chiplet or mult.

What the role involves

• Collaborate with design and architecture teams to create test plans for highly configurable IPs meant to provide interconnectivity between components across an SOC, chiplet or mult.
• Write UVM/SystemVerilog code to implement the test plan, checkers and scoreboards.
• Collaborate with software teams to define and implement configurable testbenches.
• Work with design and DV engineers to implement the test plan, debug failures, close coverage, etc.

Skills and requirements

• BS/MS in Electrical Engineering, Computer Engineering or Computer Science.
• 8+ years and current hands-on experience in block-level/IP-level/SOC-level verification.
• Proficiency in Verilog, SystemVerilog.
• Familiarity with industry-standard EDA tools for simulation and debug.

Confirmed role details

• Cambridge, England, United Kingdom (Hybrid possible inside the UK).

Candidate fit

• technical judgement, safe working habits, careful diagnostics, and practical problem-solving

Additional role context

• We are seeking a seasoned Design Verification designer with a strong background in building testbenches and writing test sequences for complex IPs.
• Play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions.