Senior Digital Verification Engineer

This Senior Digital Verification Engineer role in Edinburgh, Scotland is focused on developing verification plans from microarchitecture specifications. It would suit someone who can bring strong analytical and debugging skills to the role.

Known job details

• Location: Edinburgh, Scotland
• Work model: Hybrid
• Edinburgh, Scotland (Hybrid).
• Negotiable and competitive.
• We are seeking a Senior Digital Verification Engineer to join our Design Centre in Edinburgh.

Likely focus of the role

• Develop verification plans from microarchitecture specifications.
• Maintaining SystemVerilog/UVM verification environments.
• Define and execute test plans, UVM-SV test environments, and functional coverage.

Requirements mentioned

• Bachelor’s or higher in Electrical/Electronic Engineering (or equivalent).
• Strong experience in SystemVerilog, UVM/OVM, Specman, Verilog, C/C++, ASM, TCL/TK, Python.
• Knowledge of embedded SoC design and verification lifecycle.