Microarchitecture definition in collaboration with the broader team Preparing detailed technical documentation and presentations to stakeholders RTL Implementation, synthesis, timing closure Unit verification planning and simulation testing using SystemVerilog Delivering and validating FPGA-based lab setups for customer trials Skills & Experience Required:
A Bachelor or Master degree in electronics engineering, physics, or other relevant fields 6-8 years of relevant experience working within FPGA design Extensive hands-on industry experience of FPGA design for network applications at 100Gbps and above Experience working with PCIe, CXL, RDMA, DDR4, and high-speed transceiver technologies. Also, Ethernet, IP and bare metal systems. Comprehensive understanding of clock domain crossing (CDC) techniques would be required Strong knowledge of FPGA tool flows (synthesis, partitioning, place & route, timing analysis) Excellent skills in SystemVerilog (primarily) and also Verilog or VHDL Scripting and automation, such as TCL and Python Experience using tools such as Questa, ModelSim, GHDL, Verilator and cocotb Experience using simulation, analysis and synthesis tools such as Quartus, Vivado or Vitis Other Skills / Knowledge:
Experience in PCIe driver development Experience with embedded systems, including soft processors (Nios/Microblaze/RISC V) and SoC programming Experience with high-performance FPGA devices: Intel Agilex 7 or Xilinx Versal Premium A humble attitude and good communication skills with the ability and/or desire to mentor and support junior engineers Ability to create an understanding of complex ideas, concepts and designs to a variety of audiences from multiple backgrounds A strong and demonstrable interest in sustainable technologies, AI, ML and/or HPC would be preferred. The senior FPGA design engineer opening is based onsite in central London, 2 days per week (min). Assistance can be granted to obtain working visas.
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