The Role: We are currently seeking a Lead FPGA Design Engineer to join our Customer eXperience Engineering (CXE) team, which is part of AMD’s Adaptive and Embedded Computing Group. This is an exciting opportunity to work within a highly strategic and important part of AMD’s business, targeting the next generation of FPGA technologies and tools to meet the needs of our broad market of customers. The successful candidate will be responsible for all stages of FPGA design, such as deriving specifications, defining product architecture and development flows, RTL design, and implementation. As part of the CXE team, you will act as ‘Customer Zero’, developing full system solutions on our next generations of Adaptive SoCs/FPGAs. You will provide a customer perspective to influence the architecture of our next generation silicon and tools. You will work with leading-edge FPGA/Adaptive SoC hardware and software technologies from AMD-Xilinx, including Vivado Design Suite, Versal ACAP devices, and Evaluation cards. As a key contributor, you will work alongside a diverse and experienced design team that will enable enormous opportunities for learning and self-development. The Person: Creative innovator and thinker who loves technical problems and detail-oriented tasks. Exhibits relentless commitment to help the team meet quality and development goals on schedule. Drives to learn and perform at his or her highest potential in a technical capacity. Thrives in both a team environment and in individual contribution. Communicates openly and clearly in meetings, presentations, emails, and reports. Able to learn independently and acquire new skills required for the job. Key Responsibilities: Providing technical leadership, including mentoring junior engineers, and driving projects from initial requirements stage through to final design validation. Collaborating with Systems/Software engineers to define high-level architecture. Writing/reviewing Design Specifications and Test Plans. Developing systems targeting Adaptive SoC/FPGA at all stages of the design lifecycle. Triaging and debugging issues. Preferred Experience: In-depth knowledge of Adaptive SoC /FPGA Design, including synthesis, place and route & timing closure. Experienced with HDL (SystemVerilog/VHDL). Proven track record of developing Adaptive SoC/FPGA Designs in accordance with a formal development process. Experience providing mentorship to junior engineers. Experience with AMD-Xilinx Adaptive SoC /FPGA tools and flows. Excellent written and verbal communication skills. Familiarity collaborating with teams across geographies. Experience with scripting languages - Python, TCL or other. Academic Credentials: Bachelor’s or Master’s degree in Electronic Engineering, Computer Science, or related subject.
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